Power semiconductor device

ABSTRACT

A semiconductor device is provided in which a plurality of MOSFETs including a vertical MOSFET is formed on a substrate. The device includes a silicon carbide substrate having front and back surfaces facing each other, an isolating region formed in the substrate to extend from the front surface to the back surface of the substrate, and first and second MOSFETs formed on opposite sides of the isolating region, respectively.

FIELD OF THE INVENTION

[0001] The present invention relates to a power semiconductor deviceand, more particularly, to a power semiconductor device using a verticalpower MOSFET.

BACKGROUND OF THE INVENTION

[0002]FIG. 6 is a cross-sectional view of an n-channel vertical powerMOSFET, generally denoted at 200, using a silicon substrate.

[0003] An n-type epitaxial layer 202 is formed on an n-type siliconsubstrate 201. Two p-type body regions 203 are formed in the epitaxiallayer 202 by diffusion method. Also, an n-type doped layer 204 is formedin the each body region 203.

[0004] A source electrode 205 is formed on the n-type doped region 204.A gate electrode 207 is formed on the body region 203 provided betweenthe epitaxial layer 202 and the n-type doped region 204 through aninsulating layer 206. Also, a drain electrode 208 is formed on the backsurface of the n-type silicon substrate 201.

[0005] In the vertical power MOSFET 200, the current flowing from thedrain electrode 208 to the source electrode 205 is controlled by thevoltage supplied to the gate electrode 207.

[0006] In the vertical power MOSFET 200, the withstand voltage betweenthe source and drain electrodes is determined by the avalanche voltageof the pn junction between the p-type body region 203 and the epitaxiallayer 202. Therefore, a limitation exists in the reduction of thicknessof both body region 203 and epitaxial layer 202, because the avalanchebreakdown increases as the voltage applied to the pn junction becomeslarger. Consequently, the thickness of the vertical power MOSFET 200 isgenerally determined to about 600 μm.

[0007] On the other hand, an electrical isolation is needed betweenadjacent vertical power MOSFETs by forming an isolating region extendingfrom the front surface to the back surface of the MOSFET, when a powersemiconductor device having two vertical power MOSFETs of p-channel andn-channel formed together on the same substrate is formed. The isolatingregion is formed by the process of forming a trench which extends fromthe front surface of the MOSFET to the back surface of the substrate,and then filling the trench by silicon oxide or the like.

[0008] However, forming the narrow trench having the depth equal to thethickness of the MOSFET, e.g. 600 μm, is difficult. Consequently, it isdifficult to form a plurality of vertical power MOSFETs on the samesubstrate, and therefore, the power semiconductor device is constructedof a plurality of vertical power MOSFETs which are individuallyfabricated.

SUMMARY OF THE INVENTION

[0009] The object of the present invention is to provide a powersemiconductor devise fabricated by forming a plurality of MOSFETsincluding a vertical power MOSFET on the same substrate.

[0010] It is noticed that the breakdown voltage of silicon carbide (SiC)is about ten times that of silicon, and the band gap of silicon carbideis from twice to three times that of Silicon. As a result, it has beenfound that the thickness of a vertical power MOSFET can be made muchthinner by using a silicon carbide substrate instead of a siliconsubstrate, thus completing the present invention.

[0011] That is, the present invention provides a semiconductor devicehaving a plurality of MOSFETs, including a vertical MOSFET, formed on asubstrate, including: a silicon carbide substrate having front and backsurfaces facing each other; an isolating region formed in the substrateto extend from the front surface to the back surface of the substrate;and first and second MOSFETs formed on opposite sides of the isolatingregion, respectively.

[0012] By using the silicon carbide substrate instead of a siliconsubstrate, the breakdown voltage and the band gap of the device becomesrespectively ten times and from twice to third times that of a deviceusing a silicon substrate. Consequently, the thickness of the MOSFET canbe sufficiently smaller than that of a MOSFET using a silicon substrate,without decreasing the breakdown voltage of the pn junction between thesubstrate and the body region. Hereby, an isolating region can be formedeasily between the adjacent MOSFETs, and a plurality of MOSFETsincluding a vertical MOSFET can be formed on the same substrate.Thereby, a downsized and integrated power semiconductor device can beprovided.

[0013] The present invention also provides a semiconductor devicecharacterized in that the first MOSFET is a vertical MOSFET includingthe silicon carbide substrate of the first conductivity type; a bodyregion of second conductivity type formed on the front side of thesilicon carbide substrate; and a doped region of first conductivity typeformed in the body region, and the second MOSFET is a vertical MOSFETincluding the silicon carbide substrate of second conductivity type; abody region of first conductivity type formed on the front side of thesilicon carbide substrate; and a doped region of second conductivitytype formed in the body region, wherein the current flowing between thesilicon carbide substrate and the doped region is controlled by a gateelectrode formed on the body region in the each vertical MOSFET.

[0014] According to the present invention, two vertical MOSFETsdescribed above can be formed on the same silicon carbide substrate.

[0015] The silicon carbide substrate of the first MOSFET may include aregion with high concentration of first conductivity type impurities inthe back side of the substrate, and the silicon carbide substrate of thesecond MOSFET may include a region with high concentration of secondconductivity type impurities in the back side of the substrate.

[0016] Good ohmic contact can be obtained between the silicon carbidesubstrate and the drain electrode by forming such regions withimpurities of high concentration.

[0017] Furthermore, the common drain electrode for the first and secondMOSFETs may be formed on the back surface of the silicon carbidesubstrate.

[0018] By forming such a common drain electrode, the structure and theproducing process of the semiconductor device can be simplified.

[0019] The first and second MOSFETs preferably include a wiring layerconnecting the first and second MOSFETs on the front surface of thesilicon carbide substrate.

[0020] The producing process of the semiconductor device can be madesimpler than that of forming an additional wire such as a bonding wireor the like.

[0021] The present invention also provides a semiconductor devicecharacterized in that the first MOSFET is a vertical MOSFET includingthe silicon carbide substrate of the first conductivity type; a bodyregion of second conductivity type formed on the front side of thesilicon carbide substrate; and a doped region of first conductivity typeformed in the body region, and the second MOSFET is a vertical MOSFETincluding the silicon carbide substrate of first conductivity type; abody region of second conductivity type formed on the back side of thesilicon carbide substrate; and a doped region of first conductivity typeformed in the body region, wherein the current flowing between thesilicon carbide substrate and the doped region is controlled by a gateelectrode formed on the body region in the each vertical MOSFET.

[0022] According to the present invention, two vertical MOSFETsdescribed above can be formed on the same silicon carbide substrate.

[0023] The silicon carbide substrate of the first MOSFET may include aregion with high concentration of first conductivity type impurities inthe back side of the substrate, and the silicon carbide substrate of thesecond MOSFET may include a region with high concentration of firstconductivity type impurities in the front side of the substrate.

[0024] Good ohmic contact can be obtained between the silicon carbidesubstrate and the drain electrode by forming such regions withimpurities of high concentration.

[0025] Each of the first and second MOSFETs may be a power MOSFET havinga vertical structure.

[0026] The present invention also provides a semiconductor devicecharacterized in that the first MOSFET is a vertical MOSFET includingthe silicon carbide substrate of the first conductivity type; a bodyregion of second conductivity type formed on the front side of thesilicon carbide substrate; and a doped region of first conductivity typeformed in the body region, and the second MOSFET is a vertical MOSFETincluding the silicon carbide substrate of second conductivity type;source and drain regions of first conductivity type formed on the frontside of the silicon carbide substrate, wherein, in the first MOSFET, thecurrent flowing between the silicon carbide substrate and the dopedregion is controlled by a gate electrode formed on the body region, and,in the second MOSFET, the current flowing between the source region andthe drain region is controlled by a gate electrode.

[0027] According to the present invention, the vertical and lateralMOSFETs described above can be formed on the same silicon carbidesubstrate.

[0028] The second MOSFET is preferably a lateral MOSFET having LDDstructure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0029]FIG. 1 is a cross-sectional view of the power semiconductor deviceaccording to the first embodiment of the present invention;

[0030]FIG. 2 is a circuit diagram of the power semiconductor deviceaccording to the first embodiment of the present invention;

[0031]FIG. 3 is a cross-sectional view of the power semiconductor deviceaccording to the second embodiment of the present invention;

[0032]FIG. 4 is a circuit diagram of the power semiconductor deviceaccording to the second embodiment of the present invention;

[0033]FIG. 5 is a cross-sectional view of the power semiconductor deviceaccording to the third embodiment of the present invention; and

[0034]FIG. 6 is a cross-sectional view of the conventional verticalpower MOSFET.

DETAILED DESCRIPTION OF THE PREFFERRED EMBODIMENTS

[0035] Embodiment 1

[0036]FIG. 1 shows a cross-sectional view of a power semiconductordevice of the first embodiment according to the present invention,indicated generally at 100. The power semiconductor device 100 has ann-channel MOSFET 101 and a p-channel MOSFET 102, both formed on asilicon carbide (SiC) substrate. Each of these MOSFETs is a powerMOSFET, which has a vertical structure having source and drainelectrodes formed on the opposite surfaces of the MOSFET, respectively.The vertical power MOSFET includes DMOS (Double diffused MOS) type FET,VMOS (V-shaped gate MOS) type FET, and UMOS (U-shaped gate MOS) typeFET, for example. The MOSFET 101 and MOSFET 102 are isolated from eachother by an isolating region 103. In this case, each of the MOSFET 101and 102 is an enhancement type MOSFET.

[0037] In the n-channel MOSFET 101, an n⁻ SiC layer 2 is formed in an n⁺SiC layer 1. A plurality of p SiC body regions 3 are formed in the n⁻SiC layer 2, and an n SiC doped region 4 is formed in the p SiC bodyregion 3.

[0038] A gate electrode 6 is formed on the p SiC body region 3, which isprovided between the n⁻ SiC layer 2 and the n SiC doped region 4,through an insulating film 5 made of silicon oxide or the like. The pSiC body region 3 under the gate electrode 6 functions as a channelregion.

[0039] Also, a source electrode 7 is formed on the n SiC doped region 4.In addition, a p guard ring region 8 is formed around a plurality of pSiC body regions 3 so as to surround the p SiC body regions 3.

[0040] While the p-channel MOSFET 102 has the same structure as that ofthe n-channel MOSFET 101 except for the types of the impurities therein.

[0041] Namely, a p⁻ SiC layer 12, in which a plurality of n SiC bodyregions 13 are formed, is formed in a p⁺ SiC layer 11. Furthermore, a pSiC doped region 14 is formed in the n SiC body region 13. A gateelectrode 16 is formed on the n SiC body region 13, which is providedbetween the p⁻ SiC layer 12 and the p SiC doped region 14, through aninsulating film 15. A source electrode 17 is formed on the p SiC dopedregion 14. In addition, an n guard ring region 18 is formed around aplurality of p SiC body regions 13 so as to surround the p SiC bodyregions 13.

[0042] An isolating region 103, which is made of an insulating region106 of silicon oxide or the like, is formed between the MOSFETs 101 and102 to extend from the front surface to the back surface of the MOSFET,and isolates the MOSFETs 101 and 102 from each other. A drain electrode104 which is common to the MOSFETs 101 and 102 is formed on the backsurface of the MOSFETs 101 and 102. A protection film 105 made ofsilicon nitride or the like is partially formed on the front surface ofthe MOSFETs 101 and 102.

[0043] Because the MOSFETs 101 and 102 are made of SiC, the breakdownvoltage of the pn junction between the n⁻ SiC layer 2 and the p SiC bodyregion 3, and that of the pn junction between the p⁻ SiC layer 12 andthe n SiC body region 13 are about ten times that of the MOSFET 200using a silicon substrate. Furthermore, the band gaps of the MOSFETs 101and 102 range from twice to three times that of the MOSFET 200 usingsilicon substrate, respectively. Consequently, the breakdown voltage ofthe pn junctions are maintained as large as that of the MOSFET 200, evenif the thickness t of the MOSFETs 101 and 102 becomes sufficientlysmaller than that of the MOSFET 200. In this case, the thickness t isabout 10 μm, which is about one-fiftieth times that of the MOSFET 200.

[0044] Next, the producing method of the power semiconductor device isshortly described.

[0045] First, a non-doped SiC substrate is prepared. Then, a non-dopedSiC layer having a thickness of t is formed on the SiC substrate usingepitaxial technique.

[0046] Next, the n⁺ SiC layer 1 and the n⁻ SiC layer 2 are formed in afabrication region of the n-channel MOSFET 101 by ion implantationmethod using nitride as dopants, for example. Similarly, the p⁺ SiClayer 11 and the p⁻ SiC layer 12 are formed in a fabrication region ofthe p-channel MOSFET 102 by ion implantation method using boron asdopants, for example.

[0047] Next, the drain electrode 104 is formed on the back surface ofthe non-doped SiC substrate.

[0048] Next, the trench is formed between the MOSFETs 101 and 102 bylithography technique and dry etching technique. The trench is boredfrom the front surface of the MOSFETs 101 and 102 so that the drainelectrode 104 is exposed. For example, the width of the trench (thedistance between the two MOSFETs) is 100 μm, and the depth is 10 μm.Then, the insulating region 106 of silicon oxide or the like is formedby thermal CVD method to fill the trench. Consequently, the isolatingregion 103 is formed between the MOSFETs 101 and 102.

[0049] As described above, according to the embodiment 1, the thicknessof the MOSFETs 101 and 102 can be made about one-tenth that of a MOSFETusing a silicon substrate. This is because the MOSFETs 101 and 102 areformed on a SiC substrate instead of a silicon substrate. Consequently,the aspect ratio of the trench is so small that the formation of thetrench becomes easier than that of using a silicon substrate.

[0050] Next, the p SiC body region 3, the n SiC doped region 4, the nSiC body region 13, and the p SiC doped region 14 are formed by ionimplantation technique. Furthermore, the gate electrodes 6 and 16, thedrain electrodes 7 and 17, a wiring layer (not shown) or the like areformed. Hereby, the power semiconductor device 100 including then-channel MOSFET 101 and the p-channel MOSFET 102 integrated in the sameSiC substrate is completed.

[0051] It should be noted that a non-doped SiC substrate having athickness of t may be used instead of the non-doped SiC substrate withnon-doped SiC layer grown thereon and having a total thickness of t.

[0052]FIG. 2 is a circuit diagram of the power semiconductor device 100shown in FIG. 1.

[0053] In the power semiconductor device 100, the p-channel MOSFET 102is used as an upper arm switching element, and the n-channel MOSFET 101is used as a lower arm switching element.

[0054] The source S2 of the p-channel MOSFET 102 is connected to the Pbus line, and the S1 of the n-channel MOSFET 101 is connected to the Nbus line, respectively. Both of the D1 and D2 are connected to theexternal load. The gate G1 of the MOSFET 101 and the gate G2 of theMOSFET 102 turn on alternately, so that the load is connected to the Nor P bus line alternately. Control signals may be separately transmittedto the G1 and G2. Also, one control signal may be transmitted to thecomplementary MOS (C-MOS) with the gate G1 and gate G2. A parasiticdiode is used as a free wheeling diode (FwDi) formed between the sourceand the drain of the MOSFET.

[0055] By using three MOSFETs 100, for example, a phase switch for athree-phase-inverter can be obtained.

[0056] Embodiment 2

[0057]FIG. 3 shows a cross-sectional view of a power semiconductordevice of the second embodiment according to the present invention,indicated generally at 150, where the numerals which are identical withthose of FIG. 1 denote identical or corresponding components.

[0058] The power semiconductor device 150 has two n-channel MOSFETs 101a and 101 b, both formed on a silicon carbide (SiC) substrate. Each ofthe MOSFETs 101 a and 101 b is a vertical power MOSFET having high poweroutput.

[0059] As shown in FIG. 3, the MOSFET 101 a has the front surface onwhich elements are formed and the back surface on which a drainelectrode 104 is formed. On the other hand, MOSFET 101 b has the backsurface on which elements are formed and the front surface on which adrain electrode 107 is formed. The MOSFETs 101 a and 101 b areelectrically isolated from each other by an isolating region 103.

[0060] In the producing method of the power semiconductor device 150, anon-doped SiC substrate having a thickness of t is prepared first. Afterthe drain electrode 104 is formed on the substrate, the isolating region103 is formed by the same method as described in Embodiment 1.

[0061] Next, n type ions are implanted into a MOSFET 101 a fabricationregion through the front surface of the substrate to form an n⁺ SiClayer 1, while n type ions are implanted into a MOSFET 101 b fabricationregion through the back surface of the substrate to form an n⁻ SiC layer2.

[0062] Next, a p SiC body region 3, an n SiC doped region 4, a gateelectrode 6, a source electrode 7 or the like are formed by the samemethod as described in Embodiment 1, then the power semiconductor device150 is completed.

[0063] The thickness t of the power semiconductor device 150 is about 10μm, allowing that the isolating region 103 can be formed easily.

[0064]FIG. 4 is a circuit diagram of the power semiconductor device 150shown in FIG. 3.

[0065] In the power semiconductor device 150, the n-channel MOSFET 101 bis used as an upper arm switching element, and the n-channel MOSFET 101a is used as a lower arm switching element. Each of the MOSFETs 101 aand 101 b is an enhancement type FET.

[0066] The drain D3 of the n-channel MOSFET 101 b is connected to the Pbus line, and the S4 of the n-channel MOSFET 101 a is connected to the Nbus line, respectively. Both of the S3 and D4 are connected to theexternal load. The gate G4 of the MOSFET 101 a and the gate G3 of theMOSFET 101 b turn on alternately, so that the load is connected to the Nor P bus line alternately. A parasitic diode is used as a free wheelingdiode (FwDi) like the circuit diagram shown in FIG. 2.

[0067] Embodiment 3

[0068]FIG. 5 shows a cross-sectional view of a power semiconductordevice of the third embodiment according to the present invention,indicated generally at 160, where the numerals which are identical withthose of FIG. 1 denote identical or corresponding components.

[0069] The power semiconductor device 160 has two n-channel MOSFETs 101c and 101 d, both formed on a silicon carbide substrate. The MOSFET 101c is a vertical power MOSFET having high power output, and the MOSFET101 d is a lateral MOSFET having an offset gate.

[0070] Referring to the n-channel MOSFET 101 c, an n⁻ SiC layer 2 isformed in an n⁺ SiC layer 1. A plurality of p SiC body regions 3 areformed in the n⁻ SiC layer 2, and an n SiC doped region 4 is formed inthe p SiC body region 3.

[0071] A gate electrode 6 is formed on the p SiC body region 3, which isprovided between the n⁻ SiC layer 2 and the n SiC doped region 4,through an insulating film 5 made of silicon oxide or the like. The pSiC body region 3 under the gate electrode 6 functions as a channelregion. Also, a source electrode 7 is formed on the n SiC doped region4, and a drain electrode 104 is formed on the back surface of the n⁺ SiClayer 1.

[0072] On the other hand, in the offset-gate-type MOSFET 101 d, a p⁻ SiClayer 12 is formed in a p⁺ SiC layer 11. N⁺ SiC source/drain regions 20and n⁺ SiC regions 21 are formed in the p⁻ SiC layer 12 so that theseregions construct LDD structure. A p⁺ SiC region 22 is formed betweenthe n⁺ regions 21.

[0073] A gate electrode 26 is formed on the p⁺ SiC region 22 through aninsulating film 25 made of silicon oxide or the like, on which aninsulating film 27 made of silicon oxide or the like is formed. Also, adrain electrode 23 and a source electrode 24 are formed on the n⁺ SiCsource/drain regions 20, respectively.

[0074] An isolating region 103, which is made of an insulating region106 of silicon oxide or the like, is formed between the MOSFETs 101 cand 101 d to extend from the front surface to the back surface of theMOSFETs, isolating the MOSFETs 101 c and 101 d from each other. Aprotection film 105 made of silicon nitride or the like is partiallyformed on the surface of the MOSFETs 101 c and 10 d.

[0075] In the producing method of the power semiconductor device 160, anon-doped SiC substrate is prepared first. Then, an non-doped SiC layerhaving a thickness of t is formed on the SiC substrate using epitaxialtechnique.

[0076] Next, the n⁺ SiC layer 1 and the n⁻ SiC layer 2 are formed in afabrication region of the n-channel MOSFET 101 by ion implantationmethod using nitride as dopants, for example. Similarly, an p⁺ SiC layer11 and the p⁻ SiC layer 12 are formed in a fabrication region of thep-channel MOSFET 102 by ion implantation method using boron as dopants,for example.

[0077] Next, the drain electrode 104 is formed on the back surface ofthe non-doped SiC substrate. Then, the isolating region 103, which ismade of the insulating region 106 of silicon oxide or the like, isformed between the MOSFETs 101 c and 101 d.

[0078] Next, the MOSFET 101 c is formed by the same method as describedin Embodiment 1. Then, the MOSFET 101 d is formed by a well-known methodused for fabricating a lateral MOSFET having LDD structure.

[0079] As described above, according to the Embodiment 3, a thickness ofthe MOSFETs 101 c and 101 d can be about one-tenth that of MOSFETs usinga silicon substrate, because the MOSFETs 101 c and 101 d are formed on aSiC substrate instead of a silicon substrate. Consequently, the aspectratio of the trench is so small that the formation of the trench becomeseasier than that of using a silicon substrate.

[0080] It should be noted that a non-doped SiC substrate having athickness of t may be used instead of the non-doped SiC substrate withnon-doped SiC layer grown thereon and having a total thickness of t.

INDUSTRIAL APPLICABILITY

[0081] The present invention provides a power semiconductor devicehaving a plurality of vertical power MOSFETs, and is used as a phaseswitching element for a high voltage and/or high current inverter.

1. A semiconductor device having a plurality of MOSFETs including avertical MOSFET formed on a substrate, comprising: a silicon carbidesubstrate having front and back surfaces facing each other; an isolatingregion formed in the substrate to extend from the front surface to theback surface of the substrate; and first and second MOSFETs formed onopposite sides of the isolating region, respectively.
 2. A semiconductordevice according to claim 1, wherein the first MOSFET is a verticalMOSFET comprising the silicon carbide substrate of the firstconductivity type; a body region of second conductivity type formed onthe front side of the silicon carbide substrate; and a doped region offirst conductivity type formed in the body region, and the second MOSFETis a vertical MOSFET comprising the silicon carbide substrate of secondconductivity type; a body region of first conductivity type formed onthe front side of the silicon carbide substrate; and a doped region ofsecond conductivity type formed in the body region, wherein the currentflowing between the silicon carbide substrate and the doped region iscontrolled by a gate electrode formed on the body region in the eachvertical MOSFET.
 3. A semiconductor device according to claim 2, whereinthe silicon carbide substrate of the first MOSFET further comprises aregion with high concentration of first conductivity type impurities inthe back side of the substrate, and the silicon carbide substrate of thesecond MOSFET further comprises a region with high concentration ofsecond conductivity type impurities in the back side of the substrate.4. A semiconductor device according to claim 2, wherein a common drainelectrode for the first and second MOSFETs is formed on the back surfaceof the silicon carbide substrate.
 5. A semiconductor device according toclaim 2, wherein the first and second MOSFETs comprise a wiring layerconnecting the first and the second MOSFETs on the surface of thesilicon carbide substrate.
 6. A semiconductor device according to claim1, wherein the first MOSFET is a vertical MOSFET comprising the siliconcarbide substrate of the first conductivity type; a body region ofsecond conductivity type formed on the front side of the silicon carbidesubstrate; and a doped region of first conductivity type formed in thebody region, and the second MOSFET is a vertical MOSFET comprising thesilicon carbide substrate of first conductivity type; a body region ofsecond conductivity type formed on the back side of the silicon carbidesubstrate; and a doped region of first conductivity type formed in thebody region, wherein the current flowing between the silicon carbidesubstrate and the doped region is controlled by a gate electrode formedon the body region in the each vertical MOSFET.
 7. A semiconductordevice according to claim 6, wherein the silicon carbide substrate ofthe first MOSFET further comprises a region with high concentration offirst conductivity type impurities in the back side of the substrate,and the silicon carbide substrate of the second MOSFET further comprisesa region with high concentration of first conductivity type impuritiesin the front side of the substrate.
 8. A semiconductor device accordingto claim 1, wherein each of the first and second MOSFETs is a powerMOSFET having a vertical structure.
 9. A semiconductor device accordingto claim 1, wherein the first MOSFET is a vertical MOSFET comprising thesilicon carbide substrate of the first conductivity type; a body regionof second conductivity type formed on the front side of the siliconcarbide substrate; and a doped region of first conductivity type formedin the body region, and the second MOSFET is a vertical MOSFETcomprising the silicon carbide substrate of second conductivity type;source and drain regions of first conductivity type formed on the frontside of the silicon carbide substrate, wherein, in the first MOSFET, thecurrent flowing between the silicon carbide substrate and the dopedregion is controlled by a gate electrode formed on the body region, and,in the second MOSFET, the current flowing between the source region andthe drain region is controlled by a gate electrode.
 10. A semiconductordevice according to claim 9, wherein the second MOSFET is a lateralMOSFET having LDD structure.